1. Field of the Invention
The present invention relates to a semiconductor device comprising a transition detecting circuit and a method of activating this semiconductor device, and in particular, to an operation of reading data from a semiconductor memory device immediately after power-on.
2. Description of the Related Art
With conventional semiconductor storage devices, a chip enable signal and an address signal are input to the device before power-on. Such a conventional semiconductor storage device will be described with reference to FIG. 1. FIG. 1 is a block diagram of a conventional LSI.
As shown in the figure, an LSI 100 comprises a semiconductor storage device 200 and a transition detecting circuit 300. A power-on reset signal POR is output by an internal power supply in the LSI. The signal POR is output to the semiconductor storage device 200 and the transition detecting circuit 300 when the internal power supply (not shown) is completely initialized. Upon receiving the power-on reset signal POR, the semiconductor storage device 200 and the transition detecting circuit 300 are returned from initialization and become active. The transition detecting circuit 300 detects transitions in a chip enable signal CE and an address signal add which are externally input. Upon detecting a transition in at least one of these signals, the transition detecting circuit 300 outputs a transition detection signal TDS to the semiconductor storage device 200. Upon receiving the transition detection signal TDS, the semiconductor storage device 200 is enabled. Then, the semiconductor storage device 200 starts to operate and reads data from the semiconductor storage device 200.
However, with the configuration shown in FIG. 1, it is difficult to perform a read operation immediately after power-on. This will be described with reference to FIG. 2. FIG. 2 is a timing chart for various signals in the semiconductor device shown in FIG. 1, showing a state observed immediately after power-on.
It is assumed that the semiconductor device 100 is powered on at a time t0 as shown in the figure. Further, as described at the beginning of this section, it is assumed that a chip enable signal and an address signal are input to the semiconductor device 100 before power-on. Then, at a time t1, when the internal power supply is completely initialized, the power-on reset signal POR is enabled. Subsequently, data should be read from the semiconductor storage device 200 according to the input address signal add. However, with the conventional configuration, after the semiconductor storage device 100 has been powered on, no transitions occur in the chip enable signal or the address signal. Accordingly, the transition detecting circuit does not output a transition detection signal TDS. Thus, the semiconductor storage device 200 cannot start operations. As a result, data cannot be read from the semiconductor storage device 200.
For example, Jpn. Pat. Appln. KOKAI Publication No. 2000-339969 describes the above problems and means for solving them. With the method described in this document, while the power-on reset signal is at a specified level or higher, an enable pulse ENP is output whether or not there is a transition in the address signal. This enables a read operation to be performed immediately after power-on.
However, it may be very difficult for the method described in the above document to control the semiconductor device. That is, the enable pulse ENP rises when the voltage of the power-on reset signal reaches the specified level and then falls when the voltage decreases below the specified level. A plurality of circuit blocks included in the semiconductor device is normally returned from initialization when the power-on reset signal rises. However, it is impossible to externally determine the timing with which the power-on reset signal rises and a period for which this signal is at the specified level or higher. Consequently, it is very difficult for the circuit blocks to be returned from initialization concurrently with the power-on reset signal. In particular, the power-on reset signal often remains at the specified level or higher for only a very short time. In this case, an enable pulse may be generated before the other circuit blocks are completely returned from initialization. Then, naturally, the read operation fails. This is a serious problem particularly with semiconductor storage devices that perform destructive read operations.